Conventional communication networks include network elements (e.g., routers, bridges, gateways, switches, hubs, and/or hosts) which transmit and receive communication signals. A communication signal may include one or more components (e.g., a clock component and a set of one or more non-clock components such as a data component, a status component, and/or a control component) embodied within one or more associated signals or encoded within a single communication signal.
T-1 communication signals, for example, are synchronous communication signals each including a data component encoded utilizing one or more line codes such as pulse code modulation (PCM), Alternate Mark Inversion (AMI), Bipolar with Eight Zero Substitution (B8ZS), or the like and an independent clock component utilized in various implementations to transfer data payloads and to synchronize communication between various network elements. T-1 communication signals support full-duplex communication at signaling rates up to 1.554 Mbps utilizing a signal period of approximately 647 ns. A T-1 communication signal may also include additional non-clock components such as a Line Code Violation (LCV) component to indicate potential data component errors and/or a Loss of Signal (LOS) component to indicate the lack of an incoming signal. Other examples of communication signals having a clock component and one or more non-clock components include T-3, E-1, E-3, J-1, J-3, etc.
A typical network element includes a number of line cards coupled together via an interconnect (e.g., a mesh, one or more control cards, or the like). Each line card in turn includes: 1) a number of line interface units coupled to communication signal lines via ports for receiving and transmitting communication signals; and 2) one or more communication signal processing units to process communication signals.
FIG. 1 illustrates a portion of a network element line card according to the prior art. The illustrated line card portion includes a communication signal line interface unit 102 for each communication signal received over a number of communication signal lines 106A-106Z and a communication signal processing unit 104. Each of the communication signal line interface units 102A-102Z receives a communication signal and processes the received communication signal to extract various components (e.g., clock components 108A-108Z and non-clock components 110A-110Z). The extracted components of each received communication signal are then provided from each of the communication signal line interface units 102A-Z across a boundary, illustrated by dashed line 100, to communication signal processing unit 104.
Communication signal processing unit 104 includes a duplicate group of storage elements 112A-112Z for each of the communication signals received over communication signal lines 106A-106Z. Each group of storage elements 112A-112Z in turn includes a separate storage element for each non-clock component of its corresponding communication signal. Each group of storage elements 112A-112Z receives the extracted clock component 108A-108Z of its corresponding communication signal to control the storage and/or additional processing of the remaining non-clock components.
In the prior art embodiment illustrated in FIG. 1, one or more non-clock components 112A.A and 112Z.A (e.g., data components) from each group are then provided to a separate corresponding deframer 114A-Z and deframed while one or more remaining non-clock components 112A.D and 112Z.D (e.g., line code violation and/or loss of signal components) are provided to separate corresponding error monitoring logic 113A-Z. For each of the communication signals, the deframed communication signal may either be retained for further processing or may be immediately re-transmitted in a process known as “loopback”. A duplicate switch 116A-Z corresponding to each deframer 114A-114Z receives the deframed communication signal and provides it either to a separate jitter buffer 118A-Z for loopback or to a separate payload buffer 120A-Z for further processing.
A given deframed communication signal is stored into its respective one of the jitter buffers 118A-118Z for loopback transmission using the extracted clock component of that communication signal. A given communications signal is transmitted out of its jitter buffer using either that communication signal's extracted clock or an external clock (a clock other than a communication signal's extracted clock component). When an external clock is utilized for loopback transmission, jitter (referred to herein as “external clock jitter”) is introduced. “Jitter” is the deviation in or displacement of some aspect of the pulses in a digital signal where the deviation can be in terms of amplitude, phase timing, or the width of the signal pulse. Jitter buffers 118A-Z are utilized to buffer the communication signals prior to loopback transmission to decrease the amount of jitter present.
As illustrated in FIG. 1, storage elements, deframers, switches, jitter buffers, and payload buffers are duplicated for each received communication signal within a typical line card of a conventional network element. Similarly, each of the clock components 108A-Z and non-clock components 110A.A-110Z.D is received by communication signal processing logic 104 on a separate contact (not illustrated) across the boundary between the communication signal line interface units 102A-102Z and the communication signal processing unit 104. As the number of communication signals received per line card and/or components per communication signal increases, the amount of logic and the number of individual contacts and consequently the cost, power consumption, and “form factor” or size of communication signal processing logic 104 also increases.